----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:43:33 05/04/2012 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TOP is
generic (
		constant BIT_WIDTH : integer := 32		--DEFAULT: ONE BYTE
			);
Port ( 	


		--DAC_MON
		SCK_DAC			: OUT	STD_LOGIC;
		DIN_DAC			: OUT STD_LOGIC;
		CS_DAC			: OUT STD_LOGIC;	--active low!!
		
		SCL_MUX			: OUT STD_LOGIC;
		SDA_MUX			: INOUT STD_LOGIC;
		
		SCL_MON			: OUT STD_LOGIC;
		SDA_MON			: INOUT STD_LOGIC;
		
		SSTIN				:	OUT STD_LOGIC;
		SSPIN				:	OUT STD_LOGIC;
		RAMP				:	OUT STD_LOGIC;
		RD_ROWSEL		:	OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
		RD_COLSEL		:	OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
		RD_ENA			:	OUT STD_LOGIC;
		TST_START		:	OUT STD_LOGIC;
		TST_BOIN_CLR	:	OUT STD_LOGIC;
		SIN				:	OUT STD_LOGIC;
		SCLK				:	OUT STD_LOGIC;
		REGCLR			:	OUT STD_LOGIC;
		WR_ADDRCLR		:	OUT STD_LOGIC;
		WR_STRB			:	OUT STD_LOGIC;
		START				:	OUT STD_LOGIC;
		SAMPLESEL		:	OUT STD_LOGIC_VECTOR(5 DOWNTO 1);
		SAMPLESEL_ANY		:	OUT STD_LOGIC;
		PCLK				:	OUT STD_LOGIC;
		WR_ADVCLK		:	OUT STD_LOGIC;
		WR_ENA			:	OUT STD_LOGIC;
		CLR				:	OUT STD_LOGIC;
		SR_SEL			:	OUT STD_LOGIC;
		SR_CLOCK			:	OUT STD_LOGIC;
		SR_CLEAR			:	OUT STD_LOGIC;
		
		MON				:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
		LMON				:	OUT STD_LOGIC_VECTOR(19 DOWNTO 16);
		
		

		CLK_40M 				:  in  	STD_LOGIC;
		
		DO						:	IN		STD_LOGIC_VECTOR(16 DOWNTO 1);
		SSPOUT				:	IN		STD_LOGIC;
		RCO					:	IN		STD_LOGIC;
		TRG_16				:	IN		STD_LOGIC;
		TRG					:	IN		STD_LOGIC_VECTOR(4 DOWNTO 1);
		
		TRGIN					:	out		STD_LOGIC;	--PULSE IN
		
		TRGMON				:	IN		STD_LOGIC;
		SHOUT					:	IN		STD_LOGIC;
		TSTOUT				:	IN		STD_LOGIC;
		SW						:	IN		STD_LOGIC_VECTOR(4 DOWNTO 1)	--SWITCH ON THE UNIVERSAL EVAL BOARD.
		
	
		);
end TOP;

architecture Behavioral of TOP is
	--------------------CHIPSCOPE-----------------------------------------
	component ICON
	  PORT (
		 CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
		 CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
		 CONTROL2 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0)
		 );

	end component;

	component VIO_DAC_MON
	  PORT (
		 CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
		 CLK : IN STD_LOGIC;
--		 SYNC_IN : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
		 SYNC_OUT : OUT STD_LOGIC_VECTOR(255 DOWNTO 0));

	end component;

	component VIO_TARGET4
	  PORT (
		 CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
		 CLK : IN STD_LOGIC;
--		 SYNC_IN : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
		 SYNC_OUT : OUT STD_LOGIC_VECTOR(255 DOWNTO 0));

	end component;
	
	component ILA
	  PORT (
		 CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
		 CLK : IN STD_LOGIC;
		 TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));

	end component;
	----------------------------------------------------------------------------
	
	component multiplexer
		 Port ( CLK : in  STD_LOGIC;
				  SCL : out  STD_LOGIC;
				  SDA : inout  STD_LOGIC;
				  AMUX_S : in  STD_LOGIC_VECTOR (3 downto 0));
	end component;
	
	COMPONENT ASIC_TARGET4 
	port (
		CLK 				:  in  	STD_LOGIC;
		RESET				:	IN		STD_LOGIC;
		UPDATE			:	IN		STD_LOGIC;
		REG_DATA			:	IN		STD_LOGIC_VECTOR(362 DOWNTO 0);
		
		SCLK 				:  out 	STD_LOGIC;
		SIN 				:  out 	STD_LOGIC;
		REGCLR			:	OUT	STD_LOGIC;
		PCLK 				:  out 	STD_LOGIC
		);
	end COMPONENT ASIC_TARGET4;
	----------------------------------------------------------------------------
	
	
	SIGNAL INTERNAL_CHIPSCOPE_CONTROL_VIO_DAC_MON : STD_LOGIC_VECTOR(35 DOWNTO 0);
	SIGNAL INTERNAL_CHIPSCOPE_CONTROL_VIO_TARGET4 : STD_LOGIC_VECTOR(35 DOWNTO 0);
	SIGNAL INTERNAL_CHIPSCOPE_CONTROL_ILA : STD_LOGIC_VECTOR(35 DOWNTO 0);
	
--	SIGNAL INTERNAL_CHIPSCOPE_VIO_DAC_MON_IN : STD_LOGIC_VECTOR(127 DOWNTO 0);
	SIGNAL INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT : STD_LOGIC_VECTOR(255 DOWNTO 0);
	
--	SIGNAL INTERNAL_CHIPSCOPE_VIO_TARGET4_IN : STD_LOGIC_VECTOR(255 DOWNTO 0);
	SIGNAL INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT : STD_LOGIC_VECTOR(255 DOWNTO 0);
	
	SIGNAL INTERNAL_CHIPSCOPE_ILA_TRIG0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
	
	SIGNAL CLK_COUNTER				: UNSIGNED(15 DOWNTO 0);
	SIGNAL SCK_DAC_INTERNAL			: STD_LOGIC;
	SIGNAL DIN_DAC_INTERNAL			: STD_LOGIC;
	SIGNAL CS_DAC_INTERNAL 			: STD_LOGIC;	--ACTIVE LOW
	
	SIGNAL SCL_MUX_INTERNAL			: STD_LOGIC;
	SIGNAL SDA_MUX_INTERNAL			: STD_LOGIC;
	
	type DAC_MON_STATE_TYPE is 
		(	
			st_check_state,
			st_input_serial_data	
		);

	signal state     		: DAC_MON_STATE_TYPE := st_check_state;
	
	----------------------------------------------------------------------------
	SIGNAL rst_ASIC				: STD_LOGIC;
	SIGNAL update_ASIC			: STD_LOGIC;
	SIGNAL reg_data_ASIC			: STD_LOGIC_VECTOR(362 DOWNTO 0);
	SIGNAL SCLK_ASIC				: STD_LOGIC;
	SIGNAL SIN_ASIC				: STD_LOGIC;
	SIGNAL REGCLR_ASIC			: STD_LOGIC;
	SIGNAL PCLK_ASIC				: STD_LOGIC;
	SIGNAL TRGIN_ASIC				: STD_LOGIC;
	-----------------------TARGET4 internal DACs values-------------------------
	SIGNAL SGN_ASIC						: STD_LOGIC;
	SIGNAL Trig_type_ASIC				: STD_LOGIC;
	SIGNAL Wbias_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL TRGbias_ASIC					: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Vbias_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_16_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_15_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_14_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_13_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_12_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_11_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_10_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_9_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_8_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_7_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_6_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_5_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_4_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_3_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_2_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Trig_thresh_1_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);

	SIGNAL Vbuff_ASIC							: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL CMPbias_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL PUbias_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL VdlyN_ASIC							: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL VdlyP_ASIC							: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL MonTRGthresh_ASIC				: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL SST_SSP_out_ASIC					: STD_LOGIC;
	SIGNAL DBbias_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL SBbias_ASIC						: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Isel_ASIC							: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Vdischarge_ASIC					: STD_LOGIC_VECTOR(11 DOWNTO 0);
	SIGNAL Vdly_ASIC							: STD_LOGIC_VECTOR(11 DOWNTO 0);
	
	----------------------------------------------------------------------------
	signal toggle_TRGIN	: std_logic;
	----------------------------------------------------------------------------

begin
	----------------------------------------------------------------------------
	CHIPSCOPE_ICON : ICON
	port map (
		CONTROL0 => INTERNAL_CHIPSCOPE_CONTROL_VIO_DAC_MON,
		CONTROL1 => INTERNAL_CHIPSCOPE_CONTROL_VIO_TARGET4,
		CONTROL2 => INTERNAL_CHIPSCOPE_CONTROL_ILA
		);
		
	CHIPSCOPE_VIO_DAC_MON : VIO_DAC_MON
	PORT MAP(
		CONTROL => INTERNAL_CHIPSCOPE_CONTROL_VIO_DAC_MON,
		--CLK => CLK_COUNTER(2),	--10MHz
		--CLK => CLK_COUNTER(4),	--2.5MHz
		CLK => CLK_COUNTER(5),	--1.25MHz
--		SYNC_IN => INTERNAL_CHIPSCOPE_VIO_DAC_MON_IN,
		SYNC_OUT => INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT
	 );
	 
	CHIPSCOPE_VIO_TARGET4 : VIO_TARGET4
	  port map (
		 CONTROL => INTERNAL_CHIPSCOPE_CONTROL_VIO_TARGET4,
		 --CLK => CLK_COUNTER(2),	--10MHz
		 --CLK => CLK_COUNTER(4),	--2.5MHz
		 CLK => CLK_COUNTER(5),	--1.25MHz
--		 SYNC_IN => INTERNAL_CHIPSCOPE_VIO_TARGET4_IN,
		 SYNC_OUT => INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT
		 );
	 
	CHIPSCOPE_ILA : ILA
	  port map (
		 CONTROL => INTERNAL_CHIPSCOPE_CONTROL_ILA,
		 --CLK => CLK_COUNTER(0),	--40MHz
		 CLK => CLK_COUNTER(4),	--2.5MHz
		 --CLK => CLK_COUNTER(3),	--5MHz
		 --CLK => CLK_COUNTER(2),	--10MHz
		 TRIG0 => INTERNAL_CHIPSCOPE_ILA_TRIG0
		 );
		 
		 
	----------------------------------------------------------------------------
--	AMUX_S_I2C	: multiplexer
--		port map (
--			CLK	=> CLK_COUNTER(8), --about ?KHz
--			SCL	=> SCL_MUX_INTERNAL,
--			SDA	=> SDA_MUX_INTERNAL,
--			AMUX_S	=> INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(23 DOWNTO 20)
--		);
		
	TARGET4 : ASIC_TARGET4
		PORT MAP (
			--CLK		=> CLK_COUNTER(1),	--20MHz
			CLK		=> CLK_COUNTER(6),	--0.625MHz
			RESET		=> rst_ASIC,
			UPDATE	=> update_ASIC,
			REG_DATA	=> reg_data_ASIC,
			SCLK		=> SCLK_ASIC,
			SIN		=> SIN_ASIC,
			REGCLR	=> REGCLR_ASIC,
			PCLK		=> PCLK_ASIC	
			
		);
	----------------------------------------------------------------------------
	
	FREQ_DIV : PROCESS(CLK_40M)
	BEGIN
		IF RISING_EDGE(CLK_40M) THEN
			
			CLK_COUNTER <= CLK_COUNTER + 1;
			
		END IF;
	END PROCESS FREQ_DIV;
	
	----------------------------------------------------------------------------
	--DAC_MON CONTROL
	DAC_MON	: PROCESS(CLK_COUNTER(3))
	variable bit_counter : integer range 0 to BIT_WIDTH := 0;
	--variable cnt : integer range 0 to 7 := 0;
	variable toggle : std_logic;
	variable data_array : std_logic_vector(BIT_WIDTH-1 downto 0);
	variable dac_output_address : integer range 0 to 15 := 0;
	BEGIN
		if rising_edge(CLK_COUNTER(3)) then
			CASE state IS
				when st_check_state =>			
						
					
						if INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(12) = '1' then	--update all DAC output when it's '1', update single DAC output when it's '0'
							data_array(10 downto 8) := "100";	--control bits for the first chip(update all DACs output with the same value)
							data_array(26 downto 24) := "100";	--control bits for the second chip						
						else	--single update
							dac_output_address := to_integer(unsigned(INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(11 downto 8)));
							--> (DIN) ||firt chip 16 bits|| (DOUT)-->(DIN) ||second chip 16 bits||
							if dac_output_address <= 7 then	----Output address for fist chip (DC8 -- DC1). Daisy-chain. 
								data_array(13 downto 11) := std_logic_vector(to_unsigned(dac_output_address, 3));	--address bits
								--data_array(29 downto 27) := "000";
								data_array(10 downto 8) := "110";	--control bits(single update) for the first chip
								data_array(26 downto 24) := "000";	--control bits(no operation) for the second chip
							else	--Output address for second chip (DC16 -- DC9)
								--data_array(13 downto 11) := "000"
								data_array(29 downto 27) := std_logic_vector(to_unsigned(dac_output_address-8, 3));
								data_array(10 downto 8) := "000";	--control bits(NOP) 
								data_array(26 downto 24) := "110";	--control bits(SINGLE) 
							end if;
						end if;
						
						data_array(7 downto 0) := INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(7 downto 0);
						data_array(23 downto 16) := INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(7 downto 0);
						
						
						if INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(13) = '1' then	--to update
							CS_DAC_INTERNAL <= '0';
							state <= st_input_serial_data;
						else
							CS_DAC_INTERNAL <= '1';
							state <= st_input_serial_data;
						end if;
						
	

				when st_input_serial_data	=>
					if (bit_counter < (BIT_WIDTH)) then							
						if (toggle = '0') then
							SCK_DAC_INTERNAL <= '0';
							DIN_DAC_INTERNAL <= data_array(BIT_WIDTH-1-bit_counter);		--start from the MSB
							toggle := '1';
						else
							SCK_DAC_INTERNAL <= '1';
							toggle := '0';
							bit_counter := bit_counter + 1;
						end if;
					else
						bit_counter := 0;
						CS_DAC_INTERNAL <= '1';
						state <= st_check_state;
						
					end if;

				when others =>
					CS_DAC_INTERNAL <= '1';
					state <= st_check_state;
				END CASE;
		end if;
	END PROCESS DAC_MON;
	----------------------------------------------------------------------------
	----------------------------------------------------------------------------
	----------------------------------------------------------------------------
	SCK_DAC	<= SCK_DAC_INTERNAL;
	DIN_DAC	<= DIN_DAC_INTERNAL;
	CS_DAC	<= CS_DAC_INTERNAL;
	
	SCL_MUX	<= SCL_MUX_INTERNAL;
	SDA_MUX	<= SDA_MUX_INTERNAL;
	-------------------SIGNALS FOR TARGET4--------------------------------------
	SIN				<= SIN_ASIC;			
   SCLK				<= SCLK_ASIC;			
   REGCLR			<= REGCLR_ASIC;		
	PCLK				<= PCLK_ASIC;
	----------------------------------------------------------------------------
	--================ILA FOR DACs=====================
--	INTERNAL_CHIPSCOPE_ILA_TRIG0(0) <= CLK_40M;
--	INTERNAL_CHIPSCOPE_ILA_TRIG0(1) <= CLK_COUNTER(2);
--	INTERNAL_CHIPSCOPE_ILA_TRIG0(2) <= CLK_COUNTER(3);
--	INTERNAL_CHIPSCOPE_ILA_TRIG0(3) <= CS_DAC_INTERNAL;
--	INTERNAL_CHIPSCOPE_ILA_TRIG0(4) <= SCK_DAC_INTERNAL;
--	INTERNAL_CHIPSCOPE_ILA_TRIG0(5) <= DIN_DAC_INTERNAL;

--================ILA FOR MULTIPLEXER=====================
	--CLK_COUNTER(3);	--ILA CLK
--	INTERNAL_CHIPSCOPE_ILA_TRIG0(0) <= CLK_COUNTER(8);
--	INTERNAL_CHIPSCOPE_ILA_TRIG0(1) <= SCL_MUX_INTERNAL;
--	INTERNAL_CHIPSCOPE_ILA_TRIG0(2) <= SDA_MUX_INTERNAL;

--================================================================

--================ILA FOR TARGET4=====================
	--CLK_COUNTER(1);	--ILA CLK
	INTERNAL_CHIPSCOPE_ILA_TRIG0(0) <= CLK_COUNTER(4);
	
	INTERNAL_CHIPSCOPE_ILA_TRIG0(1) <= SCLK_ASIC;
	INTERNAL_CHIPSCOPE_ILA_TRIG0(2) <= SIN_ASIC;
	
	INTERNAL_CHIPSCOPE_ILA_TRIG0(3) <= SHOUT;	--Send the same data package twice and compare them on the chipscope for data corruption.
	--INTERNAL_CHIPSCOPE_ILA_TRIG0(3) <= rst_ASIC;
	--INTERNAL_CHIPSCOPE_ILA_TRIG0(4) <= REGCLR_ASIC;
	INTERNAL_CHIPSCOPE_ILA_TRIG0(4) <= TRGIN_ASIC;
	INTERNAL_CHIPSCOPE_ILA_TRIG0(5) <= update_ASIC;
	INTERNAL_CHIPSCOPE_ILA_TRIG0(6) <= PCLK_ASIC;
	
	--TRIGGER TESTING "TRGIN" --> "TRGMON"
	--INTERNAL_CHIPSCOPE_ILA_TRIG0(7) <= TRGMON;

--================================================================
	--settings for TARGET4 DACs from CHIPSCOPE VIO
	SGN_ASIC						<=	INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(146);
	Trig_type_ASIC				<=	INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(145);	
	
	Wbias_ASIC					<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(227 downto 216);
	TRGbias_ASIC				<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(215 downto 204);
	Vbias_ASIC					<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(203 downto 192);
	
	Trig_thresh_16_ASIC		<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(191 downto 180);
	Trig_thresh_15_ASIC		<=	INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(179 downto 168);
	Trig_thresh_14_ASIC		<=	INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(167 downto 156);
	Trig_thresh_13_ASIC		<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(155 downto 144);
	Trig_thresh_12_ASIC		<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(143 downto 132);
	Trig_thresh_11_ASIC		<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(131 downto 120);
	Trig_thresh_10_ASIC		<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(119 downto 108);
	Trig_thresh_9_ASIC		<=	INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(107 downto 96);
	Trig_thresh_8_ASIC		<=	INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(95 downto 84);
	Trig_thresh_7_ASIC		<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(83 downto 72);
	Trig_thresh_6_ASIC		<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(71 downto 60);
	Trig_thresh_5_ASIC		<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(59 downto 48);
	Trig_thresh_4_ASIC		<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(47 downto 36);
	Trig_thresh_3_ASIC		<=	INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(35 downto 24);
	Trig_thresh_2_ASIC		<=	INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(23 downto 12);
	Trig_thresh_1_ASIC		<=	INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(11 downto 0);
                           
	Vbuff_ASIC					<= INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(255 downto 244);
	CMPbias_ASIC				<= INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(243 downto 232);
	PUbias_ASIC					<=	INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(231 downto 220);
	VdlyN_ASIC					<=	INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(219 downto 208);
	VdlyP_ASIC					<= INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(207 downto 196);
	MonTRGthresh_ASIC		   <= INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(195 downto 184);
	SST_SSP_out_ASIC			<= INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(183);
	DBbias_ASIC				   <= INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(182 downto 171);
	SBbias_ASIC					<=	INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(170 downto 159);
	Isel_ASIC					<=	INTERNAL_CHIPSCOPE_VIO_DAC_MON_OUT(158 downto 147);
	
	Vdischarge_ASIC			<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(251 downto 240);
	Vdly_ASIC					<= INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(239 downto 228);
                           
	--LSB first! --> "SIN" ----> "SHOUT"
	reg_data_ASIC	<= SGN_ASIC	& Trig_type_ASIC & Wbias_ASIC	& TRGbias_ASIC & Vbias_ASIC &			
	                  Trig_thresh_16_ASIC & Trig_thresh_15_ASIC & Trig_thresh_14_ASIC & Trig_thresh_13_ASIC &
	                  Trig_thresh_12_ASIC & Trig_thresh_11_ASIC & Trig_thresh_10_ASIC & Trig_thresh_9_ASIC &	
	                  Trig_thresh_8_ASIC & Trig_thresh_7_ASIC & Trig_thresh_6_ASIC & Trig_thresh_5_ASIC &	
	                  Trig_thresh_4_ASIC & Trig_thresh_3_ASIC & Trig_thresh_2_ASIC & Trig_thresh_1_ASIC &	
							Vbuff_ASIC & CMPbias_ASIC & PUbias_ASIC & VdlyN_ASIC & VdlyP_ASIC & MonTRGthresh_ASIC &
	                  SST_SSP_out_ASIC & DBbias_ASIC &	SBbias_ASIC	& Isel_ASIC & Vdischarge_ASIC & Vdly_ASIC;
	--------------------------------------------------------------------------------------------                   			
	--RESET and UPDATE control signals from CHIPSCOPE VIO to TARGET4									
	INTERNAL_TARGET4_DACs : PROCESS(INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(255),
												INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(254)) --RESET
	BEGIN
		IF INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(255) = '1' THEN
			rst_ASIC <= '1';
			--reg_data_ASIC <= (others=>'0');
		ELSE 
			rst_ASIC <= '0';	
		END IF;
		
		IF INTERNAL_CHIPSCOPE_VIO_TARGET4_OUT(254) = '1' THEN
			update_ASIC <= '1';
		ELSE 
			update_ASIC <= '0';	
		END IF;
		
	END PROCESS INTERNAL_TARGET4_DACs;
	-----------------TARGET4 TRIGGER TESTING("TRGIN" --> "TRGMON")------------------------------------------------
	--TARGET4_TRIGGER_TEST : PROCESS(CLK_COUNTER(6)) --0.625MHz
	TARGET4_TRIGGER_TEST : PROCESS(CLK_COUNTER(8)) --0.625MHz
	BEGIN
		if rising_edge(CLK_COUNTER(8)) then	--156KHz
		--if rising_edge(CLK_COUNTER(15)) then	--about 1.22KHz
			if toggle_TRGIN = '0' then	
				
				--TRGIN <= '0';
				TRGIN_ASIC <= '0';
				toggle_TRGIN <= '1';
			else
				--TRGIN <= '1';
				TRGIN_ASIC <= '1';
				toggle_TRGIN <= '0';
										
			end if;
		end if;
		
		
	END PROCESS TARGET4_TRIGGER_TEST;
	
	TRGIN <= TRGIN_ASIC;
	
	-------------------------------------------------
	--TRIGGER TESTING "TRGIN" --> "TRGMON"
--	MON(14) <= TRGIN_ASIC;
--	MON(15) <= TRGMON;	--To watch it on the scope
	-------------------------------------------------
	
	-------------------------------------------------------------------------------------------
	TARGET4_TDC : PROCESS(CLK_150M)
	BEGIN
		if rising_edge(CLK_150M) then	
			cnt_TDC <= cnt_TDC + 1;
		end if;
		
	END PROCESS TARGET4_TDC;
	-------------------------------------------------------------------------------------------
	
	--==================SIGNALS ARE SET TO '0' FOR NOW======================================
	
   
	SCL_MON			<= '0';		 
   SDA_MON			<= '0';		
   
   SSTIN				<= '0';			
   SSPIN				<= '0';			
   RAMP				<= '0';			
   RD_ROWSEL		<= "000";	
   RD_COLSEL		<= "000000";	
   RD_ENA			<= '0';		
   TST_START		<= '0';	
   TST_BOIN_CLR	<= '0';
   
   WR_ADDRCLR		<= '0';	
   WR_STRB			<= '0';		
   START				<= '0';			
   SAMPLESEL		<= "00000";	
   SAMPLESEL_ANY		<= '0';	
   	
   WR_ADVCLK		<= '0';	
   WR_ENA			<= '0';		
   CLR				<= '0';			
   SR_SEL			<= '0';		
   SR_CLOCK			<= '0';		
   SR_CLEAR			<= '0';		
   
   --MON				<= X"0000";		
	MON				<= TRGMON & TRGIN_ASIC & "00" & X"FFF";
   LMON				<= X"F";			
	--========================================================
	end Behavioral;